The present invention is directed to the manufacturing of integrated circuits. More particularly, the invention provides a system and method for detection and prevention of one or more errors in layout designs for reticles used in the manufacture of integrated circuits manufacturing process. Merely by way of example, the invention has been applied to a reticle layout design for the manufacture of integrated circuits at a foundry operation. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Semiconductor foundries often perform fabrication of semiconductor wafers for a variety of chip manufacturers that design integrated circuits. These chip manufacturers are often called “design houses” or “fab-less” chip companies. As a general business practice, design houses supply semiconductor foundries with layout designs in electronic form. The semiconductor foundries, upon reception of layout designs, which are generally in a particular electronic format contained in a computer medium, checks the layout designs. If the layout design, or the computer medium that contains the layout design, is determined to be proper, the layout design is then used for masking for a fabrication process. The layout design is provided on one or more reticle devices, which are used by “steppers” in the foundries.
Unfortunately, certain limitations exist with conventional methods for laying out the design for the integrated circuit. For example, these designs are often expensive to provide on one or more reticles. Additionally, the designs are often complex, which lead to errors in the design or pattern provided on the reticle. Additionally, the manufacture of reticles are often time consuming and requires specialized mask shops and the like. Furthermore, complex software, which can lead to errors, is often required to develop the layout designs. These and other limitations of conventional layout techniques can be found throughout the present specification and more particularly below.
From the above, it is seen that an improved method for manufacturing integrated circuits is desired.